1. Field of the Invention
The present invention relates to a data sampling circuit and a semiconductor integrated circuit which receive an embedded clock obtained by multiplexing a clock signal and data on each other to sample it.
2. Related Art
In recent years, a certain data transmission and reception method is prevalent in a high-speed serial I/Fs (SerDes) field. In the method, a transmitting (TX) side transmits an embedded clock obtained by embedding a clock in data, and a receiving (RX) side extracts edge information of the embedded clock from a received signal, samples the data on an extracted clock edge, and restores it. A circuit which performs extraction of clock edges of an embedded clock and data sampling is called a CDR (Clock and Data Recover) circuit (see Japanese Patent Laid-Open Publication No. 357729/1992).
To restore a clock from a received signal on a receiving side, there are two available methods, one is a method of equipping a PLL in each channel and restoring both the frequency and phase of the clock, and the other is a method of equipping a phase interpolator (PI) in each channel and restoring only the phase of the clock. The latter method is commonly used.
In the latter method, all channels have only one PLL in common. The PLL supplies multiphase clocks to the PI of each channel. The PI and a phase detector form a feedback loop and generate a clock for sampling data in an embedded clock.
However, in a conventional CDR circuit, a feedback loop as described above responds slowly. If high-frequency jitter is multiplexed on an embedded clock or a phase shift suddenly occurs, the feedback loop may be unable to cope with such a change and fail to correctly take in data.